The present invention relates to an improved method for plasma etching shallow trenches and/or gate structures in the fabrication of semiconductor devices.
During the manufacture of semiconductor-based products such as integrated circuits, etching and/or deposition steps may be used to build up or remove layers of material on a semiconductor substrate. A conventional etching procedure involves the use of one or more etch gases energized into a plasma state to effect plasma etching of a layer of material. Such plasma etching has been used to provide shallow trench isolation of individual transistors in an integrated circuit. After etching the trench, the trench is filled in with a dielectric material. Commonly assigned U.S. Pat. Nos. 6,218,309 and 6,287,974 disclose a shallow trench plasma etching process.
In manufacture of transistors, it is conventional to etch the pattern of a photoresist layer into an underlying hard mask layer, strip the photoresist layer, and etch the pattern of the hard mask into a polysilicon layer down to a gate oxide layer. See, for example, U.S. Pat. No. 6,283,131. During polysilicon etch, e.g., reactive ion etching processes, the vertical profile is achieved by passivating the polysilicon lines laterally while etching the exposed polysilicon layer vertically. The lack of passivation during the etch process may lead to bowed or re-entrant polysilicon lines, undercut at the mask/polysilicon interface, as well as notching at the bottom of the polysilicon lines. At the same time, excess passivation may lead to tapered profiles and a foot at the base of the polysilicon lines.
Additionally, for dual doped applications, where different types of doping regions co-exist on a substrate, the etching behavior of the different doped regions also differs. Consequently, this may lead to profile differences which induces critical dimension variations between the differently doped regions. Furthermore, etch rate micro-loading may also occur, thereby negatively impacting gate integrity.
In view of the foregoing, there is a need for a method and apparatus to provide a proper passivation level to ensure a notch free etch profile. In addition, there is a need to mitigate profile differences and etch rate micro-loading for dual doped silicon etch processes.